Every chip inside every phone, car and server begins as an idea that must be proven correct long before it ever reaches a factory. That proving — design verification — is one of the most time-consuming stages in all of semiconductor engineering, because engineers must show that a chip will behave exactly as specified, and a bug caught after tape-out is enormously expensive to fix. A Bihar-based company has built an AI-native platform to take on exactly that bottleneck, and it carried its work onto one of India’s biggest semiconductor stages this year.
The company is Swadeza Venture, founded by Shweta Suman and built from Bihar with a simple conviction: globally relevant deep technology can be created far from India’s usual startup hubs. Suman studied engineering at BIT Mesra, spent years working in Oman, and then made the journey in the opposite direction to most — returning to Bihar after marriage and choosing to build her technology company there. Swadeza describes itself as women-led, and says its engineers average 11 years of experience across fabless semiconductors, consumer platforms and government deployments.
Swadeza’s flagship is FORGE, an AI-native semiconductor engineering platform that works across the chip lifecycle, from verification and physical design to post-silicon validation and standard cells. Its approach is deliberately different from asking a general-purpose AI assistant questions about a design. FORGE keeps the chip in a cited map, sends a language model only the information a given task touches, and converts what it learns into deterministic models — so each run is meant to finish faster and cost less than the last. And because chip designs are among a company’s most sensitive intellectual property, FORGE is deployed on-premises, inside the customer’s own environment.
The first tool in the platform, DV-FORGE, handles design verification. It reads a chip’s reference manual into a map and generates the verification plan, coverage model and UVM testbench from it. The company says DV-FORGE has already been put to work on OpenTitan-class system-on-chip designs: it signed off OpenTitan Earlgrey, a taped-out root-of-trust chip, in 30 days, finding seven bugs across roughly 40 IP blocks and 2,581 registers, and signed off its derivative, Darjeeling, in 21 days. The company also says it has run the pipeline on reference manuals from NXP, STMicroelectronics, Renesas and Infineon, and that DV-FORGE uses 80% fewer tokens than a general AI assistant.
The next tool, PD-FORGE, is being developed for physical-design closure — tracing signoff violations back to the stage that caused them. It links reports from every stage, run and tool to the same nets, across 26 Synopsys, Cadence, Siemens and open-source back-ends, and is in closed testing ahead of a production release targeted for the fourth quarter of 2026. Two further tools are in development: PS-FORGE, for post-silicon validation and debug, and SC-FORGE, which aims to produce provably optimal standard cells.
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FORGE’s first public demonstration came at SEMICON India 2026, held from 17 to 19 September under the theme “Silicon to Systems: Building the Ecosystem”. Swadeza exhibited at Startup Pod 6, and the company says it was the only startup from Bihar at the event. Swadeza was subsequently included in Forbes India’s photo coverage of the event, in the same visual showcase as IBM and Tata Electronics — a Bihar-built product sharing the frame with global semiconductor leaders. The moment arrived just two months after the Cabinet approved Semicon 2.0, a ₹1,27,500 crore second phase of India’s chip mission, and in the same year Bihar’s own cabinet approved a Semiconductor Policy 2026, with a Bihar Semiconductor Mission set up to oversee it.
Swadeza’s engineering already reaches beyond chips. The company says it built an automated AI verification system for government recruitment for the Government of Bihar, cutting turnaround from several months to weeks, and that it is building FORGE with professors from BIT Patna and with Signitude, a fabless semiconductor company. From verification to physical design and beyond, Swadeza is showing what India’s chip story looks like when it is written from Bihar — design tooling built locally, aimed at chip teams anywhere in the world.
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